RESEARCH ON TOPOLOGY AND PARAMETER DESIGN OF FAULT CURRENT LIMITER IN SMART BUILDING DC SYSTEM

Hou Jie, Gong Chunyang, Bao Jun, Wang Zhixin

Acta Energiae Solaris Sinica ›› 2023, Vol. 44 ›› Issue (5) : 88-96.

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Acta Energiae Solaris Sinica ›› 2023, Vol. 44 ›› Issue (5) : 88-96. DOI: 10.19912/j.0254-0096.tynxb.2021-1564

RESEARCH ON TOPOLOGY AND PARAMETER DESIGN OF FAULT CURRENT LIMITER IN SMART BUILDING DC SYSTEM

  • Hou Jie1, Gong Chunyang2, Bao Jun3, Wang Zhixin1
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Abstract

To protect the smart building DC system from overcurrent after short-circuit faults, a DC fault current limiter(FCL) topology is proposed in this paper. The current is rectified by the full-bridge valve and unidirectionally flows through the full-controlled power electronic switches and parallel branches. The impedance is increased by turning off the switches after fault, enabling the FCL to suppress bidirectional fault currents. The influences of FCL resistance and inductance parameters on voltage stresses and current suppression ability are analyzed. The resistance and inductance parameters of the FCL have minor effect on current limiting before operation; peak voltage stresses of diodes and power electronic switches are almost linear with FCL resistance; after the FCL operation; the current suppression effect tends to saturate with higher inductance, while increases significantly with higher resistance but is restricted by voltage stresses. The application of proposed FCL in 375 V DC system is verified via simulation in Matlab/Simulink. The results show the proposed topology can meet the fault current suppression requirements of smart building DC system.

Key words

short-circuit fault / fault protection / fault current limiter(FCL) / BIPV / smart building / low-voltage DC

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Hou Jie, Gong Chunyang, Bao Jun, Wang Zhixin. RESEARCH ON TOPOLOGY AND PARAMETER DESIGN OF FAULT CURRENT LIMITER IN SMART BUILDING DC SYSTEM[J]. Acta Energiae Solaris Sinica. 2023, 44(5): 88-96 https://doi.org/10.19912/j.0254-0096.tynxb.2021-1564

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